Job DescriptionYour responsibilities will include but not be limited to:
- Validation of an IP or feature at the SoC level.
- Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
- Learning the architecture and microarchitecture by debugging failures to the root cause.
- Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design.
- Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models.
- Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution.
Educational Qualifications:
- Must have either a BS/Btech + 5 years' experience or MS/MTech + 3 years' experience in Computer Science, Computer Engineering or Electrical Engineering.
- Minimum 2 years’ experience working on IP or SoC development, verification, or integration using System Verilog and UVM.
- Minimum 2 years’ experience with writing validation plans and software to implement those validation plans.
- Minimum 2 years’ experience with an object-oriented programming language.
- Minimum 2 years’ experience with System Verilog and UVM.
- Minimum 1 years’ experience with UNIX or Linux.
- Exposure to Graphics Verification and/or Security Verification is an advantage. Preferred Qualifications - Minimum 1 year experience with computer architecture.- Minimum 2 years’ experience with validation or testing experience, especially in a silicon design team.