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Apple SoC Physical Design Engineer PnR United States, Oregon, Beaverton 853404129
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Key Qualifications
- Minimum BS
- Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design
- Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields
- Experience with Verilog, VHDL, Python, Perl, Tcl and/or Spice is beneficial
- Currently enrolled in an undergraduate or graduate program in Computer Engineering, Electrical Engineering, Computer Science or related fields
Description
• Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.• Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals.• Timing, physical and electrical verification, and driving the signoff closure for the partitions.• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Education & Experience
Minimum BS
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