Nvidia Principal DRAM Architect – GPU Memory Solutions 

United States, California 

841125703

What You’ll Be Doing:

• Architect next-generation DRAM solutions and NVIDIA-specific implementations — including bank and stack structures, refresh mechanisms, retention schemes, ECC/CRC, power management, and reliability optimization.

• Lead innovation in high-speed memory interfaces, with deep expertise in HBM PHYs (wide I/O, TSV signaling, SI/PI, timing margins) and an understanding of GDDR/LPDDR PHY architectures.

• Collaborate across domains on advanced packaging technologies (TSVs, interposers, CoWoS, hybrid bonding, FOWLP) to optimize DRAM–GPU co-packaging for bandwidth, power, thermal performance, and yield.

• Evaluate emerging DRAM process nodes (sub-1x nm, EUV, new capacitor/dielectric materials) and their impact on density, power, retention, and cost.

• Influence industry direction by working with DRAM vendors and actively contributing to JEDEC committees, driving next-generation memory standards and NVIDIA-specific roadmap alignment.

• Model and quantify system-level trade-offs in bandwidth, latency, power, cost, yield, and thermal behavior to guide architectural decisions.

• Mentor engineers, lead technical reviews, and shape NVIDIA’s long-term memory architecture vision.
  

What We Need to See:

• MS or PhD in Electrical Engineering, Computer Engineering, Physics (or equivalent experience).

• 15+ years of experience in DRAM or memory system architecture, with at least 5+ years focused on HBM (HBM2/2e/3/3e or next-gen).

• Expertise in HBM architecture: TSV design, die stacking, interposer/CoWoS integration, refresh schemes, ECC/CRC, pseudo-channels, and thermal/power management.

• Proven participation in JEDEC or equivalent standards organizations, contributing to DRAM or HBM specifications.

• Demonstrated ability to influence DRAM vendor roadmaps, negotiate trade-offs, and enable early silicon validation.

• Strong understanding of I/O and PHY design fundamentals — timing, SI/PI, equalization, jitter budgeting.

• Proven experience balancing system-level trade-offs across performance, bandwidth, power, cost, yield, and reliability.

• Exceptional technical leadership and cross-functional communication skills.
  

Ways to Stand Out from the Crowd:

• Hands-on experience with GDDR6/7 and LPDDR5/6 architectures — including bank management, signaling, power states, and error handling.

• Deep understanding of thermal and mechanical challenges in advanced memory packaging and 3D integration.

• Familiarity with emerging memory technologies (3D DRAM, MRAM, RRAM, or next-gen hybrid memory).

• Publications, patents, or JEDEC leadership roles demonstrating influence on memory architecture and standards.

• Background in high-bandwidth computing platforms — AI, HPC, or graphics accelerators.