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Samsung DRAM Verification - Memory Team India, Karnataka, Bengaluru 604027526
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Role : Looking for Design verification Engineer with 3-5 years of experience
Responsibilities :
Good Understanding of UVM based Verification Methodology.
Develop IP level/System Level Testbench Components.
Able to develop Testplan, Checker plan and Coverage Plan based on Design Specification and requirements.
Develop Testcases , coverage bins and assertion based checkers .
Develop corner case scenario to cover the Coverage bins and achieve targeted functional coverage and code coverage.
Should be able create constrained random testcases for coverage of the design requirement.
Work closely with design engineers to achieve the Project Goal.
Take up responsibilities of complete verification of a design block.
Coordinating with other verification engineers for review and improve verification scope.
Should be able to debug any issues in the design.
Apply Verification best practises to optimize and improve overall verification.
Qualification :
Bachelors/Master Degree with 3-5 years of experience in design verification domain.
Expertise in SV,UVM and design verification methodologies.
Experience in EDA Tools , Good Hands on waveform viewer and coverage tools.
Experience in testplan , checker plan and coverage plan development.
Should be able to communicate technical details very effectively with both designers and peers.
Good Debugging and Analytical Skills.
Capability to understand DRAM JEDEC Specifications (DDR4/DDR5) and internal workings of Memory Controllers.
Understanding of next generation interconnects like PCIe Gen5, CXL is a plus.
Role : Looking for Design verification Engineer with 7+ years of experience
Responsibilities :
Architect and Develop IP level/System Level Testbench Environment using UVM.
· Employ UVM based Verification Methodology, assertions, functional/code coverage to reach verification goals.
Able to develop IP level/System Level Testplan, Checker plan and Coverage Plan based on Design Specification and requirements.
Develop assertion based checkers .
Work closely with design engineers to achieve the Project Goal.
Take up responsibilities of owning the complete verification of the IP.
Coordinating with other verification engineers for verification closure.
Should be able to support design teams in debugging any issues.
Should be able to mentor or train juniors in the overall process.
Apply Verification best practises and develop/enhance verification methodologies to optimize and improve overall verification.
Qualification :
Bachelor’s/Master’sDegree with 7-8 years of experience in design verification domain.
Capability to understand DRAM JEDEC Specifications (DDR4/DDR5) and internal workings of Memory Controllers.
Understanding of next generation interconnects like PCIe Gen5, CXL is highly desired.
Expertise in SV,UVM and design verification methodologies.
Proficiency in EDA Tools , Good Hands on waveform viewer and coverage tools.
Experience in testplan , checker plan and coverage plan development.
Should be able to communicate technical details very effectively with both designers and peers.
Good Debugging and Analytical Skills.
- Create new and improve existing verification environment
- Apply Universal VerificationMethodology (SystemVerilog/UVM)and define verification plan as well as setup verification metrics in digital environments
- Execute tests in these environments on RTL . Good debugging skills and Independent to work
- Closely cooperate with designers and team members.
DRAM Verification :
Requirement:
- Ideally 3-5 years of related work experience
- Good knowledge of SystemVerilog, Verilog
- Know-how of Unix programming languages such as Shell, TCL, Perl/Python etc
- Functional verificationexperience inUVM
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