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Apple CPU CDC/STA Engineer United States, California 821967734
18.11.2024
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Description
In this role, you will be: • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions• Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs• Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems• Working closely with EDA vendor representatives to drive improvements and new methodologies• Working closely with RTL, Verification, CAD, and Physical Design teams
Minimum Qualifications
- Minimum BS
- Scripting skills in Tcl or Perl
Preferred Qualifications
- Experience in Verilog, SystemVerilog Assertions (SVA), and Design Verification (DV) Simulations
- Experience in one or more of the following: Static Timing Analysis (STA), Clock-Domain Crossing (CDC) or Reset Domain Crossing (RDC) solutions
- Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian is a plus
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $121,900 and $183,600, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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