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Apple Design Verification Engineer United States, Texas, Austin 821471643
30.06.2025
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- Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 2 years of experience in the job offered or related occupation.
- 2 years of experience with each of the following skills is required:
- Experience working with Object Oriented Programming languages and methods.
- Integrating DV collateral from lower level testbenches.
- Enhancing and creating Python or Perl based scripts used by build and simulation flows.
- Analyzing design specifications to write complete test plans for feature functionality.
- Experience working with industry standard verification tools like Cadence (i.e. Verdi), Synopsys (i.e. VCS), or Jasper Gold.
- Knowledge and experience with design assertions and UVM checks.
- Development of test benches written in a hardware description language (i.e. VHDL, Verilog, SystemVerilog, or UVM).
- Creating verification plans from technical specs that include hardware design diagrams, state machines, and/or circuit diagrams.
- Experience with schedule tracking tools to plan project milestones and assign tasks.
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