APPLE INC has the following available in Austin, Texas. Ensure bug-free silicon for part of the SoC and IP in order to meet the required quality to make it into the testing/production. Develop detailed tests based on hardware features to verify the functionality across all possible corner-case scenarios. Develop hardware coverage plans based on the hardware micro-architecture and requirements. Develop verification methodology suitable for the particular IP, ensuring a scalable and portable test bench environment. Develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring-up, regression enabling all features under your care, and debug the test failures. Understand High-Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCle, DDR, Memory Controller Sub Systems, USB, PLL, power-up, and Secured Boot Schemes. Create coverage-driven verification plans from specifications, review, and refine to achieve coverage targets. Create an IP-level and sub-system verification plan, TB, portable test benches, sequences, and test infrastructure. Architect UVM-based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches, and test suites to the SOC level, achieving targeted coverage. Work with design, architecture, SW, FW, and external IP delivery system teams to efficiently integrate and verify the overall SOC design. Work closely with DV methodology architects to improve verification flow. 40 hours/week.