Amazon Design Verification Engineer 

United States, Texas, Austin 

47973818

The Role:
In this role you will:
· Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models
· Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
· Participate in the validation of ASIC implementations in Verilog/SystemVerilog
· Run formal verification of complex blocks to ensure functional correctness
· Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C
· Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database
Export Control Requirement:

- Bachelor's degree in Electrical / Communications Engineering or Computer Science, or related field, or equivalent experience
- 2+ years in verification preferably in communication systems
- 1+ years in UVM, C, and scripting

- Master's or Ph.D degree in Electrical / Communications Engineering
- 2+ years in digital verification, preferably in communication systems
- Familiarity with Matlab
- Modem design verification experience
- System C or Matlab model : development or DV integration experience
- Familiarity with formal verification techniques
- Strong written and verbal skills