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Intel Logic Design Engineer 
United States, California, San Jose 
818809745

Yesterday

WHO YOU ARE:

As an IP Logic Design Engineer your responsibilities will include but are not limited to:

  • Designing and/or integrating IP for Intel's Custom Silicon solutions.

  • You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation.

  • Creating a design to produce key assets that help improve product KPIs for discrete graphics products.

  • Working with SoC Architecture and platform architecture teams to establish silicon requirements.

  • Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.

  • Creating micro architectural specification document for the design.

  • Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.

  • Driving vendor's methodology to meet world class silicon design standards.

  • Architecting area and power efficient low latency designs with scalabilities and flexibilities.

  • Power and Area efficient RTL logic design and DV support.

  • Running tools to ensure lint-free and CDC/RDC clean design, VCLP.

  • Synthesis and timing constraints.

  • Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience

— or —

Master’s degree in the same fields with 2+ years of relevant experience

— or —

PhD in the same fields.

Relevant work experience should be of the following:

  • xperience with complex IP/ASIC/SOC Design Implementation.

  • Experience in system and processor architecture.

  • Experience with System Verilog/SOC development environment.


Preferred Qualifications:

  • Experience in scripting languages (i.e. PERL, TCL, or Python).

  • Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).

  • Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.

  • Experience in leading small team of engineers.

  • Experience with Industry standard protocols (i.e. PCIE, USB, DDR, etc).

  • Experience with interaction of computer hardware with software.

  • Experience with Low power/UPFimplementation/verificationtechniques.

  • Experience with Formal verification techniques.

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offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 121,050.00 USD - 227,620.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 08/31/2026