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Apple STA Engineer United States, California, Cupertino 817444042
30.03.2024
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Key Qualifications
- Have good concepts of ASIC design timing closure flow and various methodologies.
- Proven experience in ASIC timing constraints generation and timing closure. Expertise in STA tools (Primetime) and flow.
- Have concepts of timing corners/modes, process variations and signal integrity related issues.
- Hands on experience in timing/SDC constraints generation and management.
- Exposure in scripting languages (TCL and Perl).
- Have background in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer).
- Have experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing.
- Self-starter and highly motivated
Description
- As an ASIC Integration Engineer, you will have responsibilities spanning various aspects of SOC design:- Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation.- Generation of block and full chip timing constraints.- Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications.- Work with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.
Education & Experience
Bachelor's Degree + 0 years of experience
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $55.82 and $84.09/hr, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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