Marvell Senior Staff Engineer DFT 

Vietnam, Ho Chi Minh City 

812937017

What You Can Expect

• Work on all aspects of DFT (Design for Testability) for networking domain products, including architecture, testability strategy, flow, implementation, verification, and post-silicon bring-up.
• Collaborate with DFT team members for feature implementation, integration, and verification in SoCs.
• Work closely with Logic Design, Physical Design, STA, and ATE teams to ensure seamless DFT execution.

What We're Looking For

• Bachelor's/Master's degree in Electronics, Electrical Engineering or related fields and a 5 to 10 years of related professional experience in DFT.
• Strong expertise in Memory BIST with knowledge of memory testing, fault models, and BIST techniques.
• Experience in Tessent MBIST block and SoC implementation.
• Hands-on experience in MBIST simulations, production pattern generation, and mode constraints.
• Cross-functional collaboration with DFT, design, synthesis, physical design, and STA teams.
• Knowledge of JTAG (IEEE 1149.1/6 standards) and post-silicon ramp-up/debug on ATE.
• Experience with gate-level simulations (no timing & SDF-based simulations).
• Proficiency in MBIST insertion tools (Mentor Tessent preferred).
• Additional experience in SCAN, ATPG, and JTAG is a plus.
• Strong Perl/Tcl scripting skills.
• Excellent teamwork, communication, ownership, and responsibility for successful tape-out and post-silicon ramp-up.​