You will be responsible for, but not limited to:
- Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.
- Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.
- Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.
- Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies.
- Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques.
- Finds and implements corrective measures to resolve failing tests.
- Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
- Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
- Maintains and improves existing functional verification infrastructure and methodology.
- Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic.
- Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.
The Mindset We're Seeking:– You can distill complex formal verification concepts into clear, actionable insights for diverse technical audiences.
Minimum Qualifications:
You must possess a B.S. in Computer Engineering/ Electrical Engineering or any STEM Degree with 6+ years of experience listed below;
OR a M.S. in Computer Engineering/ Electrical Engineering or any STEM Degree with 4+ years of experience listed below;
OR a PhD in Computer Engineering/ Electrical Engineering or any STEM Degree with 6+ months of experience listed below.
The experience must include the following areas:
- Computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management.
- Hands on experience with industry standard formal verification tools such as JasperGold, Questa Formal, VC Formal.
- Experience with formal abstractions and other complexity reduction techniques.
- Experience with a hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools.
- Experience in assertion writing, checker development, coverage analysis, failure debug, root cause analysis.
Preferred Qualifications:
- Knowledge of Intel Architecture ISA and system architecture, x86 assembly language.
- Post-silicon debug and analysis.
- Research publications, patent filings, or other evidence of personal technical innovation in validation methodology advancement.
- Experience with applying sequential equivalence checking in complex micro-architectures.
- Programming experience in at least one language: C/C++, Perl, Python, Ruby, Java, TCL, etc.
- Intel or industry experience in pre-silicon verification of CPU cores, including specific areas of technical ownership/expertise relevant to CPUs.
Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Santa Clara, US, Texas, Austin
Position of Trustoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.