ARM Functional Safety Lead Engineer 

United States, Texas, Austin 

801254464

• Strong understanding of electronics and embedded compute systems.
• Familiarity with different IC packaging technologies and their impact on PCB design to ensure seamless integration of SoCs, ensuring proper signal routing and power delivery.
• Experience of collaborating with chip packaging teams. Ability to influence and drive SoC device pin-outs for cost optimization, routing feasibility and layer trade-off analysis.
• Detailed knowledge of high-speed design and interface standards (e.g. PCIe and DDR memory technologies). You'll analyze and optimize signal paths to ensure signal quality, minimize noise, and prevent signal degradation, especially at high speeds.
• Expertise in escape routing analysis of high density SoC's and able to provide estimates of the IO count that can be routed with a particular stack-up and design rule set.
• Extensive knowledge of Signal and Power Integrity analysis techniques from both board design and chip packaging perspectives.
• Understanding of the PCB fabrication process (PTH and HDI), stackup/VIA topologies and substrate materials. Ability to collaborate with PCB fabricators and CEMs.
• Proficiency in the use of EDA tools, specifically Cadence Allegro PCB suite and OrCAD CIS.
• Good communication and interpersonal skills. Positive can-do attitude and attention to detail.

The following skills are not essential, but experience in any of the following areas would enhance the application:

• Experience in using Signal Integrity tools from ANSYS, Siemens EDA etc.
• Experience of design automation and scripting.
• Enjoy collaborating and working in across geographies with multiple teams.