Nvidia Backend Engineer Full Chip Layout 

Romania, Iași 

783408412

What you will be doing:

• Full Chip Layout implementation and analysis of partition groups / top-level according to specifications, under challenging constraints, targeting for the area, route and integration.

• Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex layout and congestion problems.

• Daily work involves all aspects of layout implementation and analysis - DRC, LVS, ANT for partition groups and full chip level.

• Taking part inflows development.

What we need to see:

• B.SC. in Electrical Engineering/Computer Engineering.

• 4-6 years of experience as BE/LO engineer.

• Ability to quickly adapt to new technology and go deep into new areas

• Strong communication skills

• Great teammate.

• Drive new solutions based on any issues that arise

Ways to stand out from the crowd:

• Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).