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Nvidia Senior ASIC TOP Floorplan Design Engineer China, Shanghai 781609040
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What you will be doing:
Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
You will build tools and improve existing infrastructure to optimize chip area and speed of execution.
What we need to see:
Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
At least 3+ years of relevant work experience.
A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
Experience in Verilog, System Verilog or similar HVL.
Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
Python, Perl and C/C++ programming language experience.
Ways to stand out from the crowd:
Experience in driving development of large scale ASIC floorplan is a huge plus.
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