Qualcomm Signoff PDN CAD Engineer 

United States, California, San Diego 

773290677

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

This role’s responsibilities will include:

• Improving the PDN methodology for diverse Mobile, Compute, AI, IoT Snapdragon chips: accuracy of IR, EM, ESD, Thermal signoff analyses, reduction of ECO loops for EM/IR fixing, enabling hierarchicalPDN signoff, reducing the compute and memory requirement of the PDN signoff analyses.

• Developing automation and enablement of new features for the foundry advanced process nodes, collaborate with AI team on ground-breaking initiatives for compute and turn-around time reduction.

• Provide solutions to the Snapdragon design teams, analyze their requests, and address their requests through ticket queues.

• Interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirement.

• Setting up, augmenting, and maintaining a regression of complex STA and PDN designs

• Correlation of STA tools with spice, and of PDN tools with solver and spice, version-to-version validation.

• Innovating on PDN and Timing techniques and any adjacent domains, leading to participation to patents.

Preferred Qualifications:

• Bachelor’s degree or Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field.

• 1-4 years of experience in Signoff PDN or/and Timing of SoCs at either top-level or block-level.

• 1-4 years of experience with scripting tools and programming languages: Python and TCL preferred.

• Experience and exposure on PDN analysis tools such as Ansys Red-Hawk-SC (RHSC) or Cadence Voltus.

Principal Duties and Responsibilities:

• Participate to the PDN flow and features enablement for foundry advanced process nodes, at block, subsystem, and top level.

• Participate to the enablement of new methodologies and features for turn-around time reduction on various subsystems such as Modem, GPU, CPU, DDR, Camera, Video, NSP.

• Interface and drive EDA vendor Application Engineers on the resolution of Signoff problems faced by the Snapdragon design teams.

• Participate to the specification of new Signoff CAD solutions addressing the PPA requirements of the design teams.

• Deep dive on IR, EM, ESD issues, through tickets and task forces etc.

• Participate along with Qualcomm talented AI team to R&D initiatives driving differentiation in terms of compute and turn-around time.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

:

$98,500.00 - $147,700.00