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Google Senior Silicon Digital RTL Design Engineer Taiwan, New Taipei 769757278
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- 5 years of experience with Intellectual Property (IP) Development or Integration.
Preferred qualifications:
- Experience with low power design techniques such as multiple power domains, clock gating, or dynamic voltage/frequency scaling.
- Experience with Analog or Mixed Signal designs.
- Experience working with highly scaled CMOS processes, such as FinFET.
- Experience with design-for-test (DFT) flows and methodology.
- Experience in one or more scripting languages (e.g., Python, TCL, etc.).
- knowledge of version control systems such as Git.
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