Cisco ASIC Design Verification Engineer 

United States, Massachusetts 

764700986

This is an onsite role and will require working out of the Maynard, MA office location.

The ASIC DV Engineer will be working on next-generation 100G-1.6T coherent optical communications products. This role is for a senior contributor focused on verifying highly complex ASICs that are used in these next-generation systems. The role requires someone to demonstrate their experience applying sophisticated verification techniques to ASIC projects: ensuring design quality, leading sophisticated technical projects, developing process improvements, and mentoring teammates on techniques, technology & methods for verification. This role also requires significant communication skills (both written and verbal) to contribute to the ASIC projects, and working with other technical leaders in the engineering community.

This ASIC DV Engineer will need to operate independently with minimal direction in a fast-paced, dynamic, and highly technical environment creating unique verification solutions. A successful candidate will be highly self-motivated, collaborative, and passionate about delivering the most advanced high-speed optical products in the world. Knowledge of object-oriented verification methodologies is required.

• Develop detailed and comprehensive test plans
• Develop verification test benches
• Apply innovative verification techniques to complex designs
• Lead and assist with chip-level design tradeoffs by working with design engineers
• Participate and assist in FPGA emulation efforts
• Work collaboratively with the team to develop & incorporate the latest test technologies & processes

• Bachelor's degree with 7+ years of relevant experience, or a Master's degree with 4+ years, in Computer Science, Computer Engineering, or Electronic or Electrical Engineering.
• Extensive experience with the latest ASIC verification methodologies, tools, and scripting/programming languages
• Hands-on experience with C++
• Extensive experience with SystemVerilog/UVM, SystemC

• Consistent track record of innovation that leads to quantifiable improvements
• Self-motivation and the ability to implement effectively without supervision
• Knowledge of DSP algorithms and modulation techniques such as QAM is a plus
• Experience with C++ templates is a plus
• Lab silicon validation experience is a plus
• Knowledge of Formal Verification methodologies and tools such as Jasper or VCFormal is a plus