Microsoft Principal Design Verification Engineer 

United States, California, Mountain View 

762149077

Required Qualifications:

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• Design verification experience with full verification cycle on complex System on Chip(SoC) Intellectual Property(Ips) and/or systems.
• Understanding of chip and/or computer architecture with experience writing tests in

  Universal Verification Methodology (UVM) and C/C++

• Background in creating simulation environments, developing tests, and debugging designs.

Other requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:

Microsoft Cloud Background CheckThis position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Knowledge of verification principles, testbenches, stimulus generation.
• Effective communication skills.
• Ability to mentor engineers.
• Leadership and mentorship experience.
• Prior experience in the following would also be valuable:
  
  • Hardware emulation or FPGAs
  • Architecture, performance modelling or RTL design
  • Software and Firmware
  • Post-Silicon lab bringup and debug experience

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

TheMicrosoft Artificial Intelligence Silicon Engineering((AISiE)team is seeking a
Principal Design Verification engineerto deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and system on chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner.

• Own verification of complex IP(s) for the development of custom IP, Subsystem (SS) and SystemOnChip (SoC) components with focus on architectural and micro-architectural based functions and features.
• Interact with architects and design engineers to create test plans covering verification strategy, test requirements, and test environments for IP, SS, and SoC-level verification.
• Write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
• Develop Bus Functional Modesl(BFM) components to interface between test code and verification simulation environments.
• Create C and System Verilog(SV)/Universal Verification Methodology(UVM) based tests for verification.
• Collaborate across verification teams on vertical and horizontal reuse of components.
• Define and implement functional coverage and drive coverage closure.
• Triage and debug testbench, simulation, and emulation fails.
• Write makefiles and scripts for verification infrastructure.
• Apply development methodologies including code reviews, sprint planning, and feature deployment.
• Provide technical leadership through mentorship and teamwork.
• Other
  • Embody our and