Microsoft Principal Design Verification Engineer 

United States, California, Mountain View 

335448978

Required Qualifications:

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, ComputerScience, or related field AND 3+ years technical engineering experience.
• 5 years of team Leadership experience, plan and define tasks and deliverables and guide team in execution of project milestones.
• 8+ years of experience in design verification with full verification cycle on complex System on Chip(SoC) IPs and/or systems.
  • Includes verification principles, testplan development, testbench creation, stimulus generation, Universal Verification Methodology (UVM) and coverage, debugging designs as well as creating simulation environments, with full verification cycle on complex SoC IPs and/or systems.
  • Knowledge of verification principles, testbenches, stimulus generation, UVM, and coverage.
• 6+ years of experience architecting and creating robust, scalable, and extensible testbenches with Object Oriented Principles for UVM Classes, Agents, Stimulus.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Reviews Multiple-Award Schedule (MAS) documents for clarity and accuracy, meets with the Design team to critique and review, and oversees & reviews Verification Testplans and is able to efficiently direct and schedule work for the team.
• Good understanding of chip and/or computer architecture.
• Scripting language such as Python, Ruby.
• Effective communication skills.
• Prior experience in two of more of the following would also be valuable
  • System Verilog and UVM.
  • Design register-transfer level(RTL)/hardware experience.
  • Understand C compiler, C classes, Linkers, and startup scripts.
  • Firmware driver development experience.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 31, 2024.

• Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom Intellectual Property (IP) components.
• Define pre-Si verification (simulation/emulation/formal proofs/FPGA-testing ((field-programmable gate array)) and post-Silicon validation strategies.
• Work with a team to write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
• Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
• Define and implement functional coverage and drive coverage closure.
• Collaborate across verification teams on vertical and horizontal reuse of components.
• Interact with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third party vendor teams to ensure pre-and-post-Si testing is comprehensive.
• Write scripts for verification and validation infrastructure.
• Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.
• Provide technical leadership through mentor-ship and teamwork.
• Other
  • Embody our and