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Apple Design Verification Lead United States, California, Cupertino 761499229
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Key Qualifications
- Advanced knowledge of ASIC architecture, design, and verification flow.
- Expert knowledge of state-of-the-art verification flow and methodology, such as constrained random, functional/code coverage, assertions, GLS.
- Hands-on experience with modern verification languages, including SystemVerilog / UVM
- Knowledge of industry standard interfaces.
- Knowledge of Formal verification, low power verification and analog mixed signal simulation are a plus.
- Excellent social and communication skills, team spirit, and the passion to take on diverse challenges.
Description
As a CSM (Custom Silicon Management) DV lead, you will be leading the DV front for vendor silicons (power, display, touch and sensors, accessories). You will manage throughout the entire project phase, from specification, planning, execution, to sign-off. Key tasks include- Lead and track DV progress and quality. Review DV architecture, implementation, metrics. Provide technical guidance to planning, execution, and long term technology roadmap.
Education & Experience
- BS and a minimum of 10+ years of relevant industry experience is required.- MSEE / MSCE or PhD is preferred.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $160,700.00 and $282,500.00, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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