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Apple Design Verification Lead United States, California, Cupertino 120822785
18.11.2024
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Description
As a CSM (Custom Silicon Management) DV lead, you will be leading the DV front for vendor silicons (power, display, touch and sensors, accessories). You will manage throughout the entire project phase, from specification, planning, execution, to sign-off. Key tasks include- Lead and track DV progress and quality. Review DV architecture, implementation, metrics. Provide technical guidance to planning, execution, and long term technology roadmap.
Minimum Qualifications
- BS degree and 10 years of industry experience.
- Experience with modern verification languages, including SystemVerilog / UVM .
Preferred Qualifications
- Advanced knowledge of ASIC architecture, design, and verification flow.
- Expert knowledge of state-of-the-art verification flow and methodology, such as constrained random, functional/code coverage, assertions, GLS.
- Knowledge of Formal verification, low power verification and analog mixed signal simulation are a plus.
- Excellent social and communication skills, team spirit, and the passion to take on diverse challenges.
- Knowledge of industry standard interfaces.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $165,500 and $293,800, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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