Microsoft Senior Physical Design Engineer 

United States, Texas, Austin 

738117685

Required Qualifications:

• 7+ years of related technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 7+ years of experience in semiconductor design.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:
  • This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• BS/MS in Electrical or Computer Engineering or any related degree
• Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes.
• Own complete PD execution of challenging Timing & Power critical projects.
• Understanding of constraints generation, STA, timing optimization, and timing closure.
• In-depth understanding of design tradeoffs for power, performance, and area (PPA).
• Physical Design experience in synthesis to place and route of partitions through all sign-off including timing sign-off, physical verification, EMIR sign-off , Formal Equivalence, and Low Power Verification.
• Analyzing Power, Area, and Timing (PPA) trade offs for new tech nodes & enabling project level decisions. This involves from deeper understanding of circuits, metal stack analysis, Power grid planning and other aspects which influence PPA goals.
• Hands-on experience with CTS and global clock distribution methods in multi-voltage & power domain, multi-clock, and low power designs.
• Experience and knowledge of formal equivalency checks, LEC, FEV, LP, UPF, reliability, SI, and Noise.
• Experience in EDA tools such as Synopsys, or Cadence.
• Exposure and some hands-on experience with PD flows bring up/setup/flow flush, overall know how of PD-TFM and PD methodology is a big plus.
• Collaborating and influencing various aspects of PD Methodology focused on PPA.
• Proven understanding of PD construction & analysis flows and methodology.
• Understanding of constraints generation, DFT timing modes, STA analysis, Timing optimization, and Timing closure.
• Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise analysis.
• Knowledge on ECO implementation for formality and Power/Timing convergence.
• Automation skills using scripting languages such as Perl, TCL, or Python.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until August 12, 2024.

• Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
• Responsible for Timing & Power critical IPs’ execution with PPA (Power, Performance and Area) focused.
• Responsible for RTL to GDS implementation in Physical Design domain.
• Coordinate with CAD, RTL/Design teams, Architecture team, Power& Performance team, Technology team & other internal/external partners.
• Lead & Influence in TFM (Tools, Flows, and Methodology) & PPAS (Power, Performance, Area & Schedule) for design construction to signoff.
• Demonstrate technical expertise across various domains of Physical Design & Timing Signoff (E2E).
• Clear communications on project status & planning.
• Collaborate across various geographic locations based on need.
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.
• Embody our