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Amazon ASIC Physical Design Engineer - Annapurna United States, California, Cupertino 732345380
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"Utility Computing (UC)Key job responsibilities
"• Perform physical design for Amazon's machine learning custom silicon solutions
• Participate in various aspects of physical design: full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity analysis, and physical verification
• Write Tcl or PERL scripts to improve physical design flows and methods
• Collaborate with RTL, DFT designers to ensure high quality design implementation"
About the team
Diverse Experiences
AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying.Why AWS
Work/Life BalanceMentorship and Career growth
We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.Cupertino, CA, USA
"• Bachelors’ degree or higher in Electrical Engineering, Computer Engineering, or a related field with a graduation conferral date between December 2023 and September 2024
• Scripting internship/project experience with Python, Perl or equivalent
• Strong understanding of VLSI circuit design fundamentals
• Have taken at least one or more VLSI circuit design and implementation classes and done lab projects"
PREFERRED QUALIFICATIONS
"• Master’s degree in Electrical Engineering or Computer Engineering
• Previous relevant technical internship experience
• Experience with FinFET design, Clock/Power Distribution, Spice Circuit analysis
• Experience with Place and Route, digital implementation
• Experience with EDA tools from Synopsys (ICC2, DC, PT), Cadence (Genus, Innovus, Voltus)
• Experience with Verilog/SystemVerilog"
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