Qualcomm IP Standard Cell Team Front-End Characterization Engineer 

India, Karnataka, Bengaluru 

730292909

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Overview:STDCELL Characterization Engineer with 5-12 years of experience

Qualification:

• Good understanding of STDCELL Characterization using Silicon Smart or equivalent industry tool

• Understanding of different EDA view for logic library like AOCV, POCV, LVF, EM, UPF, MIS etc

• In-depth knowledge in functionality of CMOS combinatorial logic and sequential circuit and layout, and standard cell modeling, extraction and characterization.

• Experience in EDA tool/flow/methodology, product and IP developments.

• Knowledge of scripting language is mandatory (Proficient in PERL/SHELL scripting) TCL, and knowledge on SNPS tools is a plus

• The candidate needs to have strong communication and interpersonal skills to champion initiatives internally and externally.

• The candidate needs to possess Technical, analytical and cross-functional collaboration skills.

• Hands-on experience characterizing physical IPs

• Strong experience with simulation tools like Monte Carlo, Hspice, Finesim, Nanosim, Hsim etc. and Synopsys liberty format description is required.

• STDCELL IP characterization flow development

• Knowledge of the complete characterization flows, library validation and timing/ power characterization methodologies for standard cells.

• Good understanding of CMOS circuit design fundamentals

• Familiarity with Simulators (HSPICE, FineSim), understanding of schematic and parasitic extraction, liberty syntax requirements, CCS, statistical characterization, Verilog models, STA and power analysis tools.

• Hands-on experience on APL model generation for RH IR drop analysis.

• Hands-on experience on IP modeling (Verilog)

• 3P benchmarking / STA basics /comparisons at liberty level

• The candidate should have B.Tech or M.Tech in Electronics/Electrical/VLSI Design Engineering

Job Overview:

• Good understanding of digital circuits

• Hands-on experience characterizing physical Ips

• Automation skills

• Good understanding of CMOS circuit design fundamentals

• Excellent communication skills and ability to work across multiple projects is critical

Minimum Qualifications:

• 5-8 years of experience in the area of timing characterization and IP modeling (Verilog and VHDL at cell level) is required.

• APL model generation for RH IR drop analysis is required.

• AOCV/LVF working experience/understanding is required

• Hands-on experience characterizing physical IPs for advanced process geometries like 7nm, 5nm, 4nm is a must.

• Experience in the standard cell domain will be preferred (Silicon Smart/Liberate).

• Proficient in Python/PERL scripting.

• Strong experience with simulation tools like Hspice, Finesim, Nanosim, Hsim etc. and Synopsys liberty format description is required.

• Solid understanding of ASIC tapeout flows and tools like Primetime, Synopsys Design compiler, Talus, ICC is added advantage.

• Good understanding of CMOS circuit design fundamentals is highly desired.

• Excellent communication skills and ability to work across multiple projects is critical

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.