Cisco ASIC Design Verification Engineer 

Serbia, Central Serbia, Belgrade 

72754026

Responsibilities include: development of simulation models, test plan, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis. Collaborate with the hardware, software designers and vendors.

You will work with outstanding talent with vast ASIC development expertise (in design, dv, dft, physical design and post silicon validation). The team comprises of micro-architects, front-end design and verification engineers with experience ranging from 0-25 years. (we have a strong pipeline of incoming university graduates).

• Bachelor’s or Master’s degree or equivalent experience in Electrical or Computer Engineering.
• 2+years of ASIC verification experience.
• Must be proficient in System Verilog/UVM. Knowledge of Linux is critical. C/C++
• Must be familiar with ASIC design and verification processes, methodology and tools.
• Must have strong debugging skills (post-silicon lab bring-up experience is a plus).
• Expertise in Verilog/System Verilog programming.
• Deep understanding of object-oriented programming principles, constrained random stimulus, and a coverage driven verification approach.
• Scripting experience (Python, Perl, TCL, shell programming)
• Strong interactive and waveform debug skills.
• Good written and verbal communication skills.
• Collaborative and team-focused approach.

• Knowledge of Networking ASIC design verification
• Experience with formal verification (logic equivalency checking)

MSEE/CS combined with 5+ years of related experience, or BSEE/CS combined with 8+ years of related experience.

We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).