Intel Senior Layout Designer 

United States, Texas 

726993894

Job Description:

You will have the opportunity to work with partners in Technology Development (TD), Design Technology Platform (DTP), and a world class team of QnR engineers to understand, define, and execute the requirements of new trailblazing Test Chips.

Primary responsibilities include but are not limited to:

• Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bitcells, SRAMs, Register Files).
• Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.
• Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks. Uses custom auto-routers and custom placers to efficiently construct layout.
• Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests.
• Develops and drives new and innovative layout methods to improve productivity and quality.
• Troubleshoots a wide variety of issues up to and including design andtool/flow/methodologyissues used for layout design.

Additional responsibilities:

• Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies.
• Defines methodologies for hardware development related to technology node and EDA tool enabling.
• Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes.
• Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.
• Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation.
• Builds deep understanding of digital design, verification, structural and physical layout, full-chip integration, power, and performance clocking, and/or timing to enhance future TFM development.
• Collaborates with EDA vendors on defining and early testing of next-generation design tools.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

• Bachelor's degree in Electrical/Computer Engineering or related field and 6+ years of experience OR a Master's degree in Electrical/Computer Engineering or related field and 4+ years of experience OR a PhD in Electrical/Computer Engineering or related field and 2+ years of experience in:
  • Layout design & Cadence Virtuoso

Preferred qualifications:

• 6+ years of experience in:
  • CMOS VLSI design concepts, flows, and EDA tools
  • Programming/scriptingin C/C++, Python.
  • UNIX/Linux operating systems.
• 8+ years of experience in layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS).
• 4+ years of experience in EDA Tools, Flows, and Methodology (TFM) development
• 1+ year of experience with Cadence SKILL programming languages.
• Experience leading and coordinating small/medium size group of layout designers.
• Strong initiative, analytical/problem solving skills, communication skills, team working skills, ability to multitask and be able to work with a diverse team located in different geos.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, Arizona, Phoenix
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 121,050.00 USD - 227,620.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.