Microsoft Senior Design Test Engineer 

United States, California, Mountain View 

723328158

Required Qualifications:

7+ years of related technical engineering experience

• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4+ years of experience in DFT design
• 1+ years of experience using Tessent DFT tools

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:

Preferred Qualifications:

• Experience with static timing tools and timing closure
• Deep knowledge of digital design
• Understanding of analog/mixed-signal design
• Expertise in Python, Perl, or TCL scripting and C programming
• Good communication skills
• Debugging skills

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until Aug 5, 2024.

• Collaborate with design architects to engineer DFT solutions.

• Work with design and productization teams to ensure proper for stuck-at and transition fault coverage is achieved.

• Collaborate with Pysical Design (PD) team to ensure proper DFT insertion and timing closure.

• Perform scan Automatic Test Pattern Generation (ATPG) design rule checking, simulation and coverage analysis.

• Generate manufacturing test patterns.

• Perform simulation and verification of DFT patterns.

• Participate alongside IP and productization teams on silicon bring-up and characterization.

• Generate IP DFT collateral for System on Chip (SoC) integration.

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