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Google CPU Timing Closure Lead Silicon United States, California, Mountain View 713562585
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with physical design flow such as constraints, synthesis, floor planning, place and route, clock tree synthesis (CTS), or physical verification.
- Experience in high speed design timing convergence and in Static Timing Analysis tools like Primetime or Tempus.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience and understanding in engineering across timing analysis and design implementation.
- Experience in the delivery of high performance silicon in latest technology process nodes.
- Knowledge of semiconductor device physics and transistor characteristics.
- Strong scripting and data mining skills, extraction of design parameters, metrics and analyzing data trends.
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