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Google CPU Timing Convergence Lead Physical Design Silicon United States, California, Mountain View 741738282
17.06.2024
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Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Austin, TX, USA.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with Static Timing Analysis.
- Experience in high speed design timing convergence and in STA tools like Primetime or Tempus.
Preferred qualifications:
- Experience and understanding in engineering across timing analysis and design implementation.
- Experience in the delivery of high performance silicon in latest technology process nodes.
- Experience in extraction of design parameters, QoR metrics and analyzing data trends.
- Knowledge of semiconductor device physics and transistor characteristics.
- Understanding of Static Timing Analysis including sign-off corner definitions, process margining, interface timing constraints, high frequency timing convergence and setting up of frequency goals with technology scaling and PDK changes.
- Strong scripting and data mining skills.
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