Intel Senior Mixed Signal IP Logic DFX Designer United States, Texas 712974182
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The Memory IP Group (MIP) within the IP, Security, andClient ProductGroup () is looking for aDesign Engto work onIn this roleyou will workwith an experiencedMixed SignalDDR/LPDDR PHY designsgoing intoCPU and Networking products. You willbe responsible fortaking the designenabling and
Responsibilities of throle include,not limited to:
Help define DFx Scan design methodology and uarch to ensure good coverage [Scan and functional] for IP and meet products' DPM requirements
Setup and debug Spyglass-DFT or other ATPG tools, generate ATPG patterns via Mentor Graphic Tessent, RTL and GLS test validation to ensure quality design, debug and root cause stuckat and atspeed failure using Mentor GLS testbench in Synopsys VCS tools, and validate chain test in serial testbench
Define and Debug Scan Netlist insertion in Fusion Compiler.
Good and close loop communication across function group (Logic, Val, Ckt, SD, HVM) to ensure a right DFX arch introduce to the IP.
Perform yield analysis improvement and assisting the silicon debug
Analyze product requirement to balance DFX Scan requirements vs products' PPA and cost.
In addition to qualifications listed below the ideal candidate would have
Excellent analytical and problem-solving skills
Strong verbal and written communication skills
Effective team player with continuous learning mindset
Willingness to balance multiple tasks
Willingness to work in a fast-paced environment with cross functional teams.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:
Bachelor's degree in electrical engineering, Computer Engineering, or any STEM related field, with 6+ years of relevant experience, OR
Master's degree in electrical engineering, computer engineering, or any STEM related field, with 4+ years of relevant experience.
For this position, relevant experience includes working on:
Scan and/or DFX Design or Validation
IP or SoC RTL logic development, verification, or integration using Verilog/System Verilog.
RTL coding including logic and behavioral modelling.
Problem solving/debugging various simulationfailures.
Preferred Qualifications
Tools such as Tessent ATPG, Spyglass DFT, VCS and Fusion Compiler.
Knowledge of structural design concepts related to Timing, CDC/RDC(Clock/reset domain crossing), UPF (power domain modeling), LINT.
Experience with DFI/DDR/LPDDR Protocols.
Experience with DDR Phy or Memory Controller Logic Design
Experience leading RTL design execution
Structural design flows including Synthesis, Floor planning, and Speed path analysis.
Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship
Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Folsom, US, California, Santa ClaraPosition of Trust
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
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