Intel Lead SoC Physical Design Engineer 

India, Karnataka, Bengaluru 

704854611

In a fast-paced leading-edge design environment with endless possibilities of innovation and learning , you will be responsible for ensuring flawless execution in specific areas of SoC level Physical Design Implementation such as Floorplanning, Power Delivery Network Planning and implementation, SoC level Physical Integration , Physical Verification Sign-off and Tapeout, This is a great opportunity to join a team of talented individuals working on state-of-the art complex SoC Designs as part of Intel Foundry Design Services and Reference Design Development teams. The key skillsets need to include expertise in one or more areas of:� Ensuring robust design of Power Delivery Network, Decoupling Cap and Custom Route planning for complex SoC Design.� Interface with Packaging Experts to ensure planning for Bumps that meet Packaging and Manufacturing Design Rules. � Implements 3D / 2.5D IC Interface and interconnects ensuring tight correlation between Top and Bottom Die components placement along with their electrical and thermal requirements. � Generates SoC level GDS and Netlist views for consumption of downstream tools. � Physical Verification, ESD Protection planning and Verification at SoC level. � Floor planning with industry standard tools for block and SoC level complexities.� Provides timely fixes at SoC and Block level to meet Design Rules and EM-IR requirements. � Interface with multiple adjacent domain leads such as Architects, EM-IR leads, Floorplan leads, Physical Design, Verification and Packaging leads to internalize and implement changes at SoC level. The ideal candidate should exhibit behavioral traits that indicate:� Self-motivator with strong problem-solving skills� Strong leadership skills with ability to mentor junior engineers.� Excellent interpersonal skills, including written and verbal communication. � Ability to work as part of a team and collaborate in a high-paced atmosphere.� Ability to provide technical direction to the team and influence design flows and methodology.Mtech/Btech Engineering Degree in field of Electrical, Electronics, Computer Science with 8 - 10 years of relevant experience in design and methodology development of complex multi-million gate and SoC designs, with demonstrate capability in areas of :Floor-planning, Power-planning, Physical Design and Verification along with Tapeout. 2.5/3D IC Physical Design integration and Verification. Expertise in industry standard EDA tools for Floorplanning, Pand R, Layout Verification is required. Knowledge of Sign-off flows such as EM/IR , Layout Verification and ESD sign-off is an added advantage. Proficiency in scripting language, viz., Perl and Tcl would be required.We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits