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Google Power Management Validation Engineer Silicon Taiwan, New Taipei 695367175
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience developing random stress tests, silicon validation frameworks, or related infrastructure.
- Experience in one or more areas in IP level power management, DVFS, SoC/CPU/memory power management.
- Experience programming in C/C++.
- Experience with ARM architecture.
Preferred qualifications:
- Experience executing tests on emulation platforms or FPGA.
- Experience with JTAG debuggers (e.g., Lauterbach).
- Experience with board level debug.
- Experience with complex system debug, embedded operating systems and bare metal programming.
- Knowledge of OS fundamentals and low power design and architecture techniques.
- Familiarity with PMIC and power modeling techniques.
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