Intel SOC Timing Signoff Engineer 

India, Karnataka, Bengaluru 

659217697

We are looking for experienced STA engineer to drive the timing convergence of the high performance SoCs. Responsibilities include

• STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Timing analysis, and timing closure at Partition/Sub-system/FC level.
• Driving Convergence by influencing APR, Design teams stakeholders
• Familiar with Constraint development and clean up.
• Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Prime Time based ECO flows.
• Work on Automation scripts with in STA tools for Methodology development.
• Excellent debugging skills in implementation issues and ability to come up with creative solutions.
• Familiar with digital design Implementation RTL to GDSII : Synopsys/Cadence tools.

Qualifications

• 5 Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field.
• good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence
• Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA
• Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.
• Teamwork / flexibility / ability to thrive in a dynamic environment are very important

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits