Marvell Senior Staff Analog Mixed Signal IC Design Engineer 

United States, California 

657900445

As part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out

What You Can Expect

• Lead a strong technical team of emulation experts to define emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium.
• Work with various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc.
• Work closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team.
• Define and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SWdevelopment/validation
• Interface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency
• Develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
• Proven track record of managing technical teams and leading cross-functional teams for design emulation and verification.
• Substantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Seimens including extensive experience in building complex SOC emulation models
• Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM)
• Strong understanding of product development process of large SOCs and verification/debug experience in emulation platforms.
• Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc

Expected Base Pay Range (USD)

180,670 - 270,700, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at