Microsoft Senior Design Engineer 

Taiwan, Taoyuan City 

646276523

engineers to help achieve that mission.

Design Engineertechnical environment.

Qualifications

• + yearsexpertisein Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure.

• + years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs.

• + years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA)trade-offsand Post-Silicon Debug

• + experience in Designing Fabric/NetworkOnChip or Networking ASICs or Complex Control Logic

Desirable: Hands on experience in

• CPU or graphics core design.

• Complex algorithmic designs for AI usages

Ability to meet Microsoft, customer and/or government security screening requirements arefor this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will beto pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate willbe requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

You will be part of the design team driving manyof high performance, high bandwidth Network-on-Chip designs in the start-of-the-art AI SoCs. The tasks will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different subsystems. Throughout the program you will be interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec.