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Google ASIC Design Testability CAD Engineer Silicon India, Karnataka, Bengaluru 645917203
21.04.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
- 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing.
- Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
- Experience with DFT EDA tools (e.g., Tessent).
Preferred qualifications:
- 8 years of experience with DFT Design or CAD.
- Experience with DFT for subsystems with multiple physical partitions.
- Experience with Spyglass-DFT, and DFT Scan constraints, and evaluating STA paths.
- Experience in developing automated workflows using Python and Tcl.
- Experience with workflows related to ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
- Experience with DFT EDA tools like Tessent.
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