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Apple ASIC Design Integration Engineer - Pixel IP United States, California, Cupertino 639192509
13.06.2024
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Key Qualifications
- Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog.
- Industry exposure to and knowledge of ASIC/FPGA design methodology, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timing closure.
- Experience with system design methodologies that contain multiple clock domains.
- Experience in low-power design issues, tools, and methodologies including UPF power intent specification effective.
- Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
- Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with relevant scripting languages (Python, Perl, TCL).
- Good collaboration skills with strong written and verbal communication skills.
- Experience working multi-functionally with integration, design, and verification teams to specify, design, and debug digital systems
Education & Experience
Bachelor's Degree + 3 Years of Experience
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $138,900 and $256,500, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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