Intel Physical Design Engineer 

United States, Oregon, Hillsboro 

627676108

Job Description

Responsibilities include but not limited to:

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

• Analyzes results and makes recommendations to fix violations for current and future product architecture.

• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

• Optimizes design to improve product level parameters such as power, frequency, and area.

• Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications

This is an entry level position and will be compensated accordingly.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.

Minimum Qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering orany STEM related fieldwith 1+ years of relevant experience or Masters degree in Electrical Engineering, Computer Engineering orany STEM related field.

Relevant experience should include the following:

Backend design and/or integration in any of the following areas:

• Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.

• Static timing analysis constraint understanding and generation, clock stamping, and timing closure.

• Multiple Power Domain analysis using standard Power Formats UPF or CPF

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits Annual Salary Range for jobs which could be performed in the US $91,500.00-$137,436.00*Salary range dependent on a number of factors including location and experience