Cisco ASIC DFT Engineer MBIST ATPG Scan JTAG Exp 

India, Karnataka, Bengaluru 

625961823

Your Impact

• Work with the team on Verilog RTL and scripted flow implementation of the specified Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design.
• Work with the team on Verilog testbench implementation of the specified verification tests for DFT features and use case.
• Work with the team on automation scripts intended for robustness of implementation quality and improvement of efficiency.

Minimum Qualifications:

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 4 to 8 years of experience.
• Knowledge of the latest innovative trends in DFT, test and silicon engineering.
• Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

Preferred Qualifications:

• VLSI circuit physical behaviors in silicon (electrical migration, temperature/voltage variation effects).
• Basic timing concepts, including setup and hold, metastability.
• Some EDA tools usage experience
• Strong verbal communication skills and ability to thrive in a dynamic environment
• Scripting/coding language: Tcl, Python, Perl, or c/c++.

Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.