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What you’ll be doing:
You will be in charge of state of the art Design for Test/ATPG flows and implementation
Take ATPG ownership on different DFT aspects of a project, Arch & planning, pattern generation, verification and post Silicon bring up and diagnosis.
Inventing and maintaining automation flows that provide the short test time to production
What we need to see:
B.Sc. in Electrical Engineering or Computer engineering or equivalent experience
5+ years of hands on DFT/ATPG knowledge & technical experience in DFT ASIC Design and in ATPG tools
Strong programming skills in scripting languages
Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
Ways to stand out from the crowd:
Knowledge of DFT including scan, MBIST, LBIST, on-chip scan compression, fault models, ATPG, and fault simulation
Experience in Mentor TestKompress ATPG tool and retargeting flow
Programming languages: TCL, PRL, Phyton & Unix shell scripts
Experience with ATE and Silicon bring-up
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