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Google RTL Design Manager CPU Silicon Taiwan, New Taipei 612336470
24.06.2024
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
- 4 years of experience in people management, developing employees.
- Experience with CPU or AI accelerator integration with SOC.
- Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF)
Preferred qualifications:
- PhD in Electrical Engineering or Computer Science.
- Experience leading front-end design for modern processor components or AI accelerators.
- Experience with ARM Instruction Set Architecture.
- Experience with SOC design, architect, and integration.
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