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What you'll be doing:
Work as part of a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions.
Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
Participate in establishing physical design methodologies, flow automation, floorplan, power/clock distribution, IP and toplevel P&R, and timing closure.
Drive the physical implementation of custom digital IPs from conception to layout using industry standard tools and custom design flows.
Create prototypes of patentable ideas on test chips and drive them to be deployed across the entire line of products.
Collaborate with cross-functional teams to improve the performance and reliability of NVIDIA's next generation products through custom circuit solutions and detailed transistor-level analysis.
What we need to see:
BSEE (MSEE preferred) or equivalent experience.
3+ years of experience in large VLSI physical design implementation on 5nm, 4nm and/or 3nm technology.
Successful track record of delivering designs to production is a requirement.
Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys(ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics.
Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/route and tapeout solutions.
To be successful you should possess strong analytical and debugging skills required.
Proficiency using Python, Perl, Tcl, Make scripting is helpful.
Good understanding of process issues and digital circuit design techniques.
Strong understanding of transistor level fundamentals.
Hands on experience running Spice simulations, EM/IR analysis, and some transistor level timing analysis
You will also be eligible for equity and .
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