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Apple SoC Memory Performance Engineer Platform Architecture United States, Oregon, Beaverton 590843144
02.05.2024
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Key Qualifications
- Solid knowledge of cache management and memory controller for DRAM technologies. Prior experience on writing a cache and memory simulator using C++ is a big plus.
- Excellent C/C++/scripting coding, debug, and testing skills.
- Papers published in top computer architecture conferences/journals and filed patents related to computer architecture, demonstrating ability of designing and evaluating different cache and memory performance techniques
- Prior work on analyzing the memory access patterns and bandwidth/latency requirements of CPU, GPU, Video, Camera, Machine Learning hardware accelerators or similar areas.
- Expertise in cooperative code development using a revision control system such as GIT.
- Strong communication and documentation skills.
Description
- C++ performance modeling of proposed architectural solutions and features.- Gathering, analyzing, and validating measured and simulated results to compare architectural design alternatives.- Carefully analyze and present results to enable data specific architecture/design.- Measure and analyze existing SoC and workloads.- Some international travel is required for this position.
Education & Experience
BS and a minimum of 10 years relevant industry experience.
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