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Google Platform Memory Controller Architect Silicon Taiwan, New Taipei 585294574
17.07.2024
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in a memory controller architecture/micro-architecture.
- Experience in ASIC architecture performance analysis, tools, and simulators at different abstraction levels (e.g., Cycle Accurate, TLM, or Functional).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with coding in C/C++/Python.
- Experience working with third-party vendor solutions.
- Experience designing/implementing or validating RTL for Fabric, MMUs, Caches, or memory controllers.
- Knowledge of HDL languages such as System Verilog, Verilog.
- Knowledge of Coherent interconnects, Caches, or memory system.
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