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Apple CAD Engineer - PDV United States, California, Sunnyvale 584869343
18.11.2024
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Description
- Develop, improve and maintain various aspects of physical verification flow and methodology- Coordinate the effort of validating flows, improving for custom checks and data generation- Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Minimum Qualifications
- Knowledge of Silicon chip design flows
- DRC/LVS debug experience in various technology nodes
- Scripting experience in programming languages such as Python, Perl or Tcl
- Experience with flow automation and development
- Minimum requirement of BS and 0+ years of relevant industry experience.
Preferred Qualifications
- Knowledge in Calibre/ICV/Pegasus runset coding for DRC/LVS
- Knowledge of parasitic extraction, SKILL coding or PnR tools is a plus
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $121,900 and $183,600, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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