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Apple CAD Engineer - PDV United States, Texas, Austin 886869543
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Description
- Develop, improve and maintain various aspects of physical verification flow and methodology- Coordinate the effort of validating flows, improving for custom checks and data generation- Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Minimum Qualifications
- Knowledge of Silicon chip design flows
- DRC/LVS debug experience in various technology nodes
- Scripting experience in programming languages such as Python, Perl or Tcl
- Experience with flow automation and development
- Minimum requirement of BS and 0+ years of relevant industry experience.
Preferred Qualifications
- Knowledge in Calibre/ICV/Pegasus runset coding for DRC/LVS
- Knowledge of parasitic extraction, SKILL coding or PnR tools is a plus
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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