Amazon Sr Silicon ATE Engineer Project Kuiper 

United States, California, Sunnyvale 

562683218

The Role:
As Senior Silicon ATE Test Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment.You’ll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You’ll be part of the team that creates a chip and system test infrastructure and methodology applicable to transmit and receive communication systems.In this role you will:
 Write test plans and test programs for SoCs tested on Teradyne and Advantest equipment. Run test vectors on test platforms and optimize tester and vector parameters to ensure timing and repeatability.
 Work with ASIC design teams ensure the test equipment and processes required for production meet Amazon standards for high-volume manufacturing.
 Review load board, socket, and probe card designs and simulation results for best layout practices and possible signal / power integrity issues.
 Optimize equalization settings for 30+ Gpbs SERDES running on ATE platforms.
 Actively identify test related readiness, issues, and optimizations throughout the product lifecycle and work towards expedient resolutions.
 Assist in qualification activities such as burn-in board design, HTOL, ESD, etc.
 Conduct failure analysis and drive issue resolutions as well as close potential test gaps and correlations issues throughout the supply and manufacturing chains.Export Control Requirement:

 Bachelor's degree in electrical/communications engineering or related field, or equivalent experience.
 7+ years of experience in High Speed Digital Test Engineering, preferably in high-volume consumer devices manufacturing.
 Strong written and verbal skills.
International travel required during release to production phases.

 Experience with digital / SERDES test techniques such as scan, MBIST, and loopback.
 Experience with JTAG and boundary-scan techniques.
 Understand of and experience with DFT and DFM.
 Experience with ATE hardware development and debugging.
 Experience with running firmware on DUTs to reduce test time and increase self-testability.
 Knowledge of PCB design requirements and layout best practices for high-speed signaling.
 Excellent understanding of wireless electronic manufacturing, assembly and test processes, and hands on experience with failure analysis.
 Knowledgeable in production control processes, statistical analysis platforms (Galaxy, Spotfire, JMP or similar), data interpretation/analysis, Cp/Cpk, and bench/tester correlation.
 Working Knowledge of scripting languages such as Python, PERL, and Tcl/Tk