As a member of Analog Design team in Japan LSI Design Center in Tokyo, you will have the responsibility for Design/Productize Analog ICs.
Minimum Qualifications
Transistor-level feasibility studies for various kinds of Analog circuits such as High-speed serial interface, PLLs, and Analog peripherals (OSC, Bias, LDO)
Designing blocks and documenting design towards formal design reviews.
Collaborate with layout designer for circuit design, including layout parasitic and mismatch.
Top-level simulations to validate chip-level integration.
Experience in Mixed-signal simulation.
Building design spec by negotiating with cross-functional team.
Test planning for evaluation and production.
Analyzing ATE/Lab measurement results and suggesting further steps.
Good knowledge of device physics as it applies to analog IC designs.
University Degree (MSEE is of preference) in relevant field of specialization.
Preferred Qualifications
Create High-speed link-budget and specification definition for PHY.
Create block-level specifications based on link-budget and transistor-level feasibility.
Design and simulate transistor-level design of PHY high-speed block.
Good knowledge of common high-speed serial interface standards.
Experience in behavioral modeling to assess different architectures.
Knowledge of ESD.
Business level or higher for Japanese and English communication.