In this role, the key responsibilities are the followings:- Create High-speed link-budget and specification definition for PHY- Create block-level specifications based on link-budget and transistor-level feasibility- Perform transistor-level feasibility studies for various blocks in Rx/Tx/Clk generation- Design and simulate transistor-level design of PHY high-speed blocks- Collaborate with layout designers for overall circuit design including layout parasitic and mismatch.- Document design and simulation results for formal design review process.- Define production / bench-level test plans for production / evaluation.